1. Technical Field
The present disclosure relates to semiconductor memory devices and, more particularly, to a bit line sense amplifier circuit for use in a semiconductor memory device and a control method thereof capable of preventing or substantially reducing the sense amplifier circuit from floating, and a coupling effect, with a precise data sensing.
2. Discussion of Background and Summary
Recent rapid development of the semiconductor industry has brought about a large capacity and high performance in semiconductor memory devices. This means a number of elements adapted in the semiconductor memory device provide a large capacity and high performance. In particular, the high performance of a sense amplifier used in the semiconductor memory device is becoming more important.
More specifically, bit line sense amplifiers relating to data sense and amplification require items of relatively higher performance than earlier devices.
The bit line sense amplifier circuit adapted for use in a semiconductor memory device is used for a general operation such as a data read or write operation to a memory cell, and senses and amplifies read or write data and outputs the read or write data to the external or memory cells.
Qualities required in the sense amplifier circuit may be a high-level sensitivity, high-speed operation, wide operating range of power source voltage, low power consumption, small substrate area space and the like. Of these, the sense amplifier circuit needs a more precise data sensing operation based on a high sensitivity, because the semiconductor memory devices are achieving higher performance.
The sense amplifier circuit for the semiconductor memory device has been researched with several solutions to obtain the precise data sensing operation based on high sensitivity. More specifically, when the semiconductor memory device is not under an active state of read or write operation, no power is applied to the sense amplifier circuit such that the sense amplifier circuit becomes in a floating state. Then, the sense amplifier circuit causes several problems, such as erroneous operation. According to the necessity to prevent the floating state in the sense amplifier circuit, a precharge circuit has been introduced.
The precharge circuit is to supply a given level of voltage to the sense amplifier circuit, so that the sense amplifier circuit is not floated when the sense amplifier circuit is not in an active state, that is, when no power is applied thereto. The given level of voltage is called a precharge voltage, and the sense amplifier circuit is indicated as having a precharge state.
A bit line sense amplifier adapted for use within the semiconductor memory device comprises at least one PMOS sense amplifier unit including plural PMOS transistors and at least one NMOS sense amplifier unit including plural NMOS transistors. The PMOS and NMOS sense amplifier units may have a cross-coupled sense amplifier type. Also, the sense amplifier circuit comprises a plurality of NMOS transistors receiving a given level of voltage for precharging.
To execute the active operation, such as a read or write operation in the semiconductor memory device, a sense amplifier enable signal is provided to enable a plurality of sense amplifier units of the sense amplifier circuit. The sense amplifier units perform a sense and amplification operation in response to the sense amplifier enable signal.
On the other hand, when the semiconductor memory device does not perform the active operation, the sense amplifier enable signal of the sense amplifier circuit is disabled. In this case, the precharge signal is enabled. A precharge voltage having a given level of voltage is supplied to the sense amplifier circuit in response to the precharge signal.
As described above, a given level of precharge voltage is applied to the sense amplifier circuit not undergoing the active operation, thus, the sense amplifier circuit is prevented from being in a floating state. At this time, the state of the sense amplifier circuit is called a precharge state.
The sense amplifier circuit is well known to those of ordinary skill in the art, thus, a further detailed description thereof is omitted herein.
FIG. 1 illustrates timings for the operation of a conventional bit line sense amplifier circuit.
As shown in FIG. 1, a time point when a bit line precharge signal BLP generated in a bit line precharge circuit within the bit line sense amplifier circuit is disabled is ‘t1’. A time point when a sense amplifier precharge signal SAP is disabled in response to the bit line precharge signal BLP is ‘t2’. A time point when a word line enable signal WL for an active state of the sense amplifier circuit 100 is enabled is ‘t3’. A time point when a sense amplifier enable signal LAPG/LANG is enabled by the word line enable signal WL is ‘t4’.
The bit line precharge signal BLP of the bit line precharge circuit in the semiconductor memory device is disabled by an applied active command. The sense amplifier precharge signal SAP is disabled in response to the disabled bit line precharge signal BLP. Then, a word line is enabled in response to the word line enable signal WL. After the word line enable signal WL is enabled and a given time lapses, the sense amplifier enable signal LAPG/LANG is enabled.
At this time, between the point of time when the word line enable signal WL is enabled and the point of time when the sense amplifier enable signal LAPG/LANG is enabled, a voltage appears between bit lines BL/BLB. That is, data of a memory cell is developed through the bit line.
For a time interval between a time point ‘t2’, when the precharge state is completed, and a time point ‘t4’, when the sense amplifier enable signal LAPG/LANG is enabled, the sense amplifier circuit 100 is in the floating state. That is, even though the sense amplifier circuit 100 includes a sense amplifier precharge circuit, it is in the floating state between times ‘t2’ and ‘t4’.
In the time interval of ‘t2’ to ‘t4’, a voltage is developed and a voltage level between the bit lines BL/BLB is changed. As the voltage development effect occurs between the bit lines BL/BLB, a coupling effect occurs between the drain and source of the PMOS and NMOS transistors within the plurality of sense amplifier units connected with the bit lines BL/BLB. This is why the sense amplifier circuit has a floating state during the time interval between ‘t2’ and ‘t4’.
The coupling effect increases a potential of the plurality of sense amplifier units and, as a result, interrupts a precise sensing operation of the bit line sense amplifier circuit, causing a drop of sensing level.
Accordingly, exemplary embodiments of the present invention provide a bit line sense amplifier circuit for use in a semiconductor memory device and a control method thereof. The bit line sense amplifier circuit can be prevented from having a floating state. A coupling effect of the bit line sense amplifier circuit can be prevented or substantially reduced, and a precise data sensing of the bit line sense amplifier circuit can be obtained.
According to an exemplary embodiment of the present invention, a bit line sense amplifier circuit for use in a semiconductor memory device is characterized in that the bit line sense amplifier circuit is controlled to maintain a precharge state thereof until a point of time when a sense amplifier enable signal to enable the sense amplifier circuit is applied.
A precharge completion time point of the sense amplifier circuit may occur later by a given time than a precharge completion time point of a bit line connected to the sense amplifier. A sense amplifier precharge signal to control a precharge of the sense amplifier circuit may be a signal generated in the sense amplifier circuit itself, in response to the sense amplifier enable signal. The sense amplifier precharge signal may be an inverted signal of the sense amplifier enable signal. The sense amplifier precharge signal of the sense amplifier circuit may be generated and applied in a specific signal generating circuit adapted to be outside the sense amplifier circuit.
The sense amplifier circuit may comprise a sense amplifier for performing a sensing and amplification operation of data in response to the sense amplifier enable signal, and a sense amplifier controller for controlling a precharge state of the sense amplifier unit in response to a sense amplifier precharge signal.
The sense amplifier may comprise at least one PMOS sense amplifier unit including a plurality of PMOS transistors cross-coupled with one another to amplify data; at least one NMOS sense amplifier unit including a plurality of NMOS transistors cross-coupled with one another to amplify data; and at least one PMOS transistor and at least one NMOS transistor for receiving respective sense amplifier enable signals to enable the sense amplifier units.
The sense amplifier controller may comprise at least one inverter for receiving the sense amplifier enable signal and outputting a sense amplifier precharge signal having an opposed state to the sense amplifier enable signal; and a plurality of NMOS transistors that applies a precharge voltage level to the sense amplifier when the sense amplifier precharge signal is enabled, and that does not apply the precharge voltage level to the sense amplifier when the sense amplifier precharge signal is disabled.
The precharge voltage level of the sense amplifier may be the same as a bit line precharge voltage level. The precharge voltage level may be ½ of the power voltage level.
According to an exemplary embodiment of the present invention, a method of controlling a bit line sense amplifier circuit for use in a semiconductor memory device comprises a first step of enabling a sense amplifier precharge signal and maintaining a precharge state of the sense amplifier circuit; a second step of starting an active operation of the sense amplifier circuit, and applying a sense amplifier enable signal of the sense amplifier circuit to sense a bit line; and a third step of disabling the sense amplifier precharge signal in response to the sense amplifier enable signal.
An applied time point of the sense amplifier precharge signal may be later by a given time than an applied time point of the bit line precharge signal. The sense amplifier precharge signal may be a signal generated in the sense amplifier circuit itself in response to the sense amplifier enable signal. The sense amplifier precharge signal may be an inverted signal of the sense amplifier enable signal. The sense amplifier precharge signal may be generated and applied in a specific signal generating circuit adapted to be outside the sense amplifier circuit.
According to an exemplary embodiment of the present invention, a method of generating a sense amplifier precharge signal to precharge a bit line sense amplifier circuit comprises controlling an enable or disable state of the sense amplifier precharge signal, depending upon a sense amplifier enable signal controlling an operation of the sense amplifier circuit.
The sense amplifier precharge signal may be an inverted signal of the sense amplifier enable signal.
According to exemplary embodiments of the present invention as described above, a bit line sense amplifier circuit for use in a semiconductor memory device can prevent the sense amplifier circuit from becoming in a floating state, and a coupling effect can be prevented or substantially reduced, with precise data sensing and amplification.